By Ron Wilson

What’s at stake:
Increasingly systems houses, rather than chip companies, are designing the silicon for their systems and optimizing it for their workloads. Their needs are altering the traditional chip design flow.

Two closely linked changes in the semiconductor industry are gradually altering the way ICs are designed, demanding new skills from designers, inspiring new tools from the EDA industry, and opening new roles for AI in the design flow. In a recent conversation with Synopsys VP for Product Management and System Solutions Tom De Schutter we explored this evolution.

By Ron Wilson

What’s at stake:
With all the talk of chiplets, it is important to have a perspective on what the real issues are, and where the industry stands with them. Looking into it, we find three categories of answers.

Chiplets, systems in package, multi-die modules — there is a whole new vocabulary growing up around the old idea of putting more than one die into an IC package. By now the words, the technologies they represent, and the supply chains necessary to achieve them are resolving into three main categories, all under the general heading of multi-die modules (MDM).

The first category — well represented by recent massive GPU and datacenter CPU designs — best fits the acronym SiP. The second category — just emerging today — we might call decomposed SoCs. And the third category — arguably still several years away — we can properly call chiplet-based systems. To define each of these, we should discuss the issues that separate them and the issues they have in common.

By Ron Wilson

What’s at stake:
With 3nm processes barely in production, the industry is already talking about 2nm — and sliding the schedules. With a whole new kind of transistor and massive technical challenges, 2nm will be a heavy lift not only for the foundries, but for the EDA companies that have to support it and the customers who have to design for it.

Almost drowned out by the shouting about chiplets, the so-called 2nm process node — the next full step after 3nm — is moving toward production. It promised developers of CPUs, GPUs, AI chips and, eventually, smartphone application processors, a whole lot more transistors, a little less power consumption — if designers are very careful — and a lot more hard work.

But what is the reality? When is 2nm coming? How is it different from 3nm? And what has to happen to make 2nm a useable process for actual chip designers?

By Ron Wilson

What’s at stake:
Ideally, chiplets could be off-the-shelf products that snap together like building blocks — no EDA tools required. Anyone who could specify exactly what they wanted could create a system-in-package implementation, opening up silicon to a far wider range of designers, and, incidentally, undermining parts of the EDA and design-services industries. Could it ever really happen?

One early conception of chiplets — in their formative days within the US Department of Defense — was of an open market. You could buy the functions you needed off the shelf, arrange them into a multi-die assembly, and after verification and analysis have a finished hardware design. Later thinking took this idea ever further. What if you could, figuratively speaking, just snap the chiplets together like building blocks, with no complex design automation tools or analyses needed, and could be sure that the resulting assembly would work correctly?

By Ron Wilson

What’s at stake:
Arm’s public offering could be a chance to invest in the explosive growth of artificial intelligence. Or investors could be buying into a total misunderstanding of Arm and what it does — whether AI takes off or not.

No recent tech IPO has stirred as much discussion as Softbank’s plan to float about ten percent of Arm Ltd. on the US NASDAQ exchange. Although Softbank has quietly backed off from their initial suggestions about an offering price, the figures still imply earnings growth close to that of Nvidia. That is, astronomical.

By Ron Wilson

What’s at stake:
What lies in the future for chiplets? They could change the structure of the semiconductor industry, freeing it from the geriatric grip of Moore’s Law and the hegemony of three giant manufacturers. Or they could, like thin-film hybrids and multidie packages before them, withdraw into a few application niches where their challenges are manageable and their costs acceptable.

By Ron Wilson

What’s at stake?
Advanced semiconductor packaging are neither routine nor affordable. But if they were, the industry could experience the triggering of an avalanche of chiplets, allowing IP vendors to sell silicon, erase many of the advantages of rich design teams and disaggregate the IC supply chain.

Many dies in one package. This is getting to be the topic of the month in the industry. But there are several subjects interdigitated in this area, and they are rapidly getting tangled together. This article combs them out by examining three different but related topics: multiple dies in a package; advanced packaging and; chiplets.