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Truth & Consequences

Getting to the Bottom of Backside Power Delivery

The expected early adopters of Backside Power Delivery (BPD) are also early users of multi-die advanced packaging and chiplets. But the two technologies — BPD and chiplets — may not play well together. So, what to do?
Getting to the bottom of Backside Power Delivery
Comparison of frontside and backside Power Delivery Networks (PDNs) (Source: IMEC)

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By Ron Wilson

What’s at stake:
Backside Power Delivery is being promoted by all three foundry majors. It has advantages, but will substantially complicate wafer processing and multi-die module design, with undetermined costs to users. Intel, TSMC, and, more faintly, Samsung are singing the praises of backside power delivery (BPD). Recently, Synopsys raised their voice in harmony, pledging support for TSMC’s efforts. But what is BPD, what does it imply, and who, outside the giant foundry trio, really cares?

This story begins a decade ago, when foundries began drilling tiny holes deep into wafers and then thinning the wafers — grinding away the back side of the wafer until the remainder was thin enough to expose the bottom of the hole. Filled with conductive material, the hole became a via — an electrical path from the front side to the back side of the wafer. This allowed connections on the back of the wafer for easier packaging and die stacking.


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