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Tale of High-NA EUV Lithography: Two Paths Diverged

One branch of the fork, supported by TSMC, relies on double patterning to solve the resolution problem. The other branch of the fork, now pursued by Intel, relies on a new generation of EUV lithography systems with higher resolution.
Two Paths Diverged: Tale of High-NA EUV Lithography
Intel Oregon receives the delivery of a key component of ASML’s first TWINSCAN EXE:5200 system – an extreme ultraviolet (EUV) high-volume production system with a 0.55 numerical aperture – as part of the two companies’ long-term High NA collaboration framework. (Source: Intel)

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By Ron Wilson

What’s at stake:
The leading edge of the semiconductor industry is struggling mightily to reach what they have named the Angstrom era. The phrase refers to an arbitrary point, somewhere around the so-called 3 nm process node, where it becomes fashionable to name technology nodes in Angstroms rather than in nanometers — hence, not 1.5 nm but 15 Angstroms. It is at about this point that the requirements for ever more detailed patterns on silicon wafers exceed the capabilities of today’s EUV lithography systems and procedures.

It is possible with great care nowadays to print patterns on the surface of a wafer in which the lines are about 13 nm apart — just fine enough for today’s so-called 5 nm processes. These patterns are projected onto a layer of radiation-sensitive material — a photoresist layer, so-called for mostly historical reasons. The pattern is then developed, and transferred through rather tortuous etching and cleaning processes to temporary layers of material that lie just beneath the resist. These layers, in turn, form a hard barrier through which material can be etched away, or added to the surface of the wafer to form the transistors and wires that make up the IC.

For the 3 nm generation, the most critical layers — such as those that make electrical connections to the transistors or that make up the first levels of metal interconnect — will require resolution just slightly finer than 13 nm in order to make connections to the most closely packed transistors. That is beyond the capabilities of today’s EUV systems with today’s procedures.

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