By Ron Wilson
For chiplet-based system design to spread beyond a few major CPU and GPU vendors, SoC designers will have to confront a host of unfamiliar challenges. As always it will fall to the EDA industry to bridge the gap between what today’s SoC design teams know and what will be required for them to succeed at multi-die design.
The Ojo-Yoshida Report spoke with Shekhar Kapoor, senior director of product line management at Synopsys, who is at the center of the action as the EDA industry gears up for chiplet-based design.
Kapoor says that the EDA industry is committed to ensuring that their customers can scale from large single-die SoCs today to multi-die systems incorporating perhaps hundreds of chiplets tomorrow. That will demand collaboration across the entire IC ecosystem: collaboration between foundries, IP developers, and EDA companies, new specialized tool vendors, packaging designers and manufacturers, and assembly and test houses. “Having the right tools is one element in making this happen,” Kapoor suggests, “but having cooperation across the ecosystem is another.”
But can even this level of collaboration make a single, SoC-like flow for multi-die assemblies happen? Kapoor believes it can. Already tools have integrated — tools such as synthesis are already aware of issues like layout, timing, and power. Kapoor says that even more aspects of multi-die design must be brought forward to early in the design process, and that complexities like Multiphysics analysis must be effectively hidden from all but a few sign-off experts. “A customer told us there are no new 3D engineers being born,” Kapoor quotes. “We have to enable the engineers we have.”
When will all this happen? Kapoor puts us between the crawl and walk stages of tool evolution. The point tools exist today to succeed with a 3D multi-die design, if you have the experts to use them. The EDA industry is automating the work of those experts, so they will only be needed at sign-off. And AI, in the form of intelligent design-space exploration using reinforcement learning, will play a huge role in helping design teams to manage the vast design paces and multidimensional optimizations beginning even at the architectural planning level.
Finally, will this work lead to an open market for chiplets, like today’s electronics distributors? Kapoor believes this can happen in some specific areas narrow enough to limit variations in design teams’ wish lists. But in general, he sees a general store for chiplets being a long way into the future.
The Synopsys video podcast can be viewed via the Ojo-Yoshida Report Channel of YouTube. That video is embedded below.
Ron Wilson is a contributing editor for The Ojo-Yoshida Report. He contracts with Intel, but the views are his, not Intel’s.
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