By Ron Wilson
One of the foremost questions in chiplet-based system design is interconnect: how to get signals between the chiplets. This question spans many layers of issues, from substrate choice to interface design to physical placement to test plans and control of unintended coupling between dies. But choices at these many layers interact. Integrating the tools for them is a work in progress, and design teams’ ability to deal gracefully with these challenges will determine the success or failure of the eventual vision: an open, off-the-shelf chiplet market.
These insights are courtesy of Toni Mastroianni, advanced packaging solutions director at Siemens EDA. The Ojo-Yoshida Report interviewed him for our Dig Deeper—Chiplets podcast series.
Interface choice will dictate the number and spacing of I/O pads on the chiplets. But that in turn will influence floorplanning for both the chiplets and the substrate, which will influence each other.
Mastroianni emphasizes that all levels of the interconnect question must be addressed early in the design planning phase, because decisions made for individual issues can influence other decisions. For example, the choice of substrate material will have many implications across the design. The choice of interface standards will also have many effects. Depending on the substrate and the required bandwidth, signals between chiplets may be carried over ordinary source-synchronous interfaces or PHY-based serial channels such as UCIe or BoW.
Interface choice will dictate the number and spacing of I/O pads on the chiplets, But that in turn will influence floorplanning for both the chiplets and the substrate, which will influence each other, as designers try to get PHY IP blocks placed on the chiplets in a way that minimizes interconnect path length on the substrate. These interactions will only get more complex as third-party chiplet vendors enter the market with predefined I/O placements.
Exacerbating the challenge, the timing tools necessary for validating timing for the I/O connections come from two different domains: chip-level tools from IC EDA, and substrate-level tools from packaging design flows. Integrating them is a work in progress.
But just getting signals between chiplets is only part of the problem, Mastroianni warned. Test, for one, creates another set of issues. Known good dies (KGDs) are not enough. In most cases, chiplets will have to be fully testable even after they have been assembled onto the substrate and packaged — after many key signals have become inaccessible to the outside world.
This requires another level of test planning — to ensure that the combination of built-in self-test and external access can fully test each die once inside the package, that the interconnect signals necessary for the test sequences meet timing, and that parallel test does not result in voltage droop or unacceptable heating. Again, interactions between challenges, often requiring cooperation between disparate tools.
And there are the unintended interactions between chiplets as well. Mastroianni warned in particular of thermal coupling, and of mechanical stress — some of it caused by thermal expansion — that can compromise the system. These interactions must be recognized, modeled, and simulated from early in design planning, he emphasized. Once again, the multiphysics analysis tools necessary for the job exist and work well, but they are quite different from normal chip EDA tools.
Integration of the tools into a single user interface will be necessary.
Integration of the tools into a single user interface will be necessary. But even so, there will be culture shock. Many of these issues are entirely new to most chip design teams. It will require not only tool integration, but also training and coaching to make familiar all the facets that must go into even early planning.
The two fundamental pillars of this integration and education effort will be open standards and collaboration between EDA competitors, and between EDA, chiplet, and packaging vendors, Mastroianni said. This is the charter of the Chiplet Design Exchange (CDX) program within the Open Compute Project.
We broadcasted the discussion with Toni Mastroianni. The full video is available on the Ojo-Yoshida channel on YouTube for you to catch up!
Ron Wilson is a contributing editor for The Ojo-Yoshida Report. He contracts with Intel, but the views are his, not Intel’s.
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